
adjacency-matrix:     file format elf64-littleaarch64


Disassembly of section .init:

0000000000400540 <_init>:
  400540:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  400544:	910003fd 	mov	x29, sp
  400548:	9400003c 	bl	400638 <call_weak_fn>
  40054c:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400550:	d65f03c0 	ret

Disassembly of section .plt:

0000000000400560 <.plt>:
  400560:	a9bf7bf0 	stp	x16, x30, [sp, #-16]!
  400564:	b0000090 	adrp	x16, 411000 <__FRAME_END__+0x100a0>
  400568:	f947fe11 	ldr	x17, [x16, #4088]
  40056c:	913fe210 	add	x16, x16, #0xff8
  400570:	d61f0220 	br	x17
  400574:	d503201f 	nop
  400578:	d503201f 	nop
  40057c:	d503201f 	nop

0000000000400580 <__libc_start_main@plt>:
  400580:	d0000090 	adrp	x16, 412000 <__libc_start_main@GLIBC_2.17>
  400584:	f9400211 	ldr	x17, [x16]
  400588:	91000210 	add	x16, x16, #0x0
  40058c:	d61f0220 	br	x17

0000000000400590 <__gmon_start__@plt>:
  400590:	d0000090 	adrp	x16, 412000 <__libc_start_main@GLIBC_2.17>
  400594:	f9400611 	ldr	x17, [x16, #8]
  400598:	91002210 	add	x16, x16, #0x8
  40059c:	d61f0220 	br	x17

00000000004005a0 <abort@plt>:
  4005a0:	d0000090 	adrp	x16, 412000 <__libc_start_main@GLIBC_2.17>
  4005a4:	f9400a11 	ldr	x17, [x16, #16]
  4005a8:	91004210 	add	x16, x16, #0x10
  4005ac:	d61f0220 	br	x17

00000000004005b0 <puts@plt>:
  4005b0:	d0000090 	adrp	x16, 412000 <__libc_start_main@GLIBC_2.17>
  4005b4:	f9400e11 	ldr	x17, [x16, #24]
  4005b8:	91006210 	add	x16, x16, #0x18
  4005bc:	d61f0220 	br	x17

00000000004005c0 <__isoc99_scanf@plt>:
  4005c0:	d0000090 	adrp	x16, 412000 <__libc_start_main@GLIBC_2.17>
  4005c4:	f9401211 	ldr	x17, [x16, #32]
  4005c8:	91008210 	add	x16, x16, #0x20
  4005cc:	d61f0220 	br	x17

00000000004005d0 <printf@plt>:
  4005d0:	d0000090 	adrp	x16, 412000 <__libc_start_main@GLIBC_2.17>
  4005d4:	f9401611 	ldr	x17, [x16, #40]
  4005d8:	9100a210 	add	x16, x16, #0x28
  4005dc:	d61f0220 	br	x17

00000000004005e0 <putchar@plt>:
  4005e0:	d0000090 	adrp	x16, 412000 <__libc_start_main@GLIBC_2.17>
  4005e4:	f9401a11 	ldr	x17, [x16, #48]
  4005e8:	9100c210 	add	x16, x16, #0x30
  4005ec:	d61f0220 	br	x17

Disassembly of section .text:

00000000004005f0 <_start>:
  4005f0:	d280001d 	mov	x29, #0x0                   	// #0
  4005f4:	d280001e 	mov	x30, #0x0                   	// #0
  4005f8:	aa0003e5 	mov	x5, x0
  4005fc:	f94003e1 	ldr	x1, [sp]
  400600:	910023e2 	add	x2, sp, #0x8
  400604:	910003e6 	mov	x6, sp
  400608:	580000c0 	ldr	x0, 400620 <_start+0x30>
  40060c:	580000e3 	ldr	x3, 400628 <_start+0x38>
  400610:	58000104 	ldr	x4, 400630 <_start+0x40>
  400614:	97ffffdb 	bl	400580 <__libc_start_main@plt>
  400618:	97ffffe2 	bl	4005a0 <abort@plt>
  40061c:	00000000 	.inst	0x00000000 ; undefined
  400620:	00400e40 	.word	0x00400e40
  400624:	00000000 	.word	0x00000000
  400628:	00400e68 	.word	0x00400e68
  40062c:	00000000 	.word	0x00000000
  400630:	00400ee8 	.word	0x00400ee8
  400634:	00000000 	.word	0x00000000

0000000000400638 <call_weak_fn>:
  400638:	b0000080 	adrp	x0, 411000 <__FRAME_END__+0x100a0>
  40063c:	f947f000 	ldr	x0, [x0, #4064]
  400640:	b4000040 	cbz	x0, 400648 <call_weak_fn+0x10>
  400644:	17ffffd3 	b	400590 <__gmon_start__@plt>
  400648:	d65f03c0 	ret
  40064c:	00000000 	.inst	0x00000000 ; undefined

0000000000400650 <deregister_tm_clones>:
  400650:	d0000080 	adrp	x0, 412000 <__libc_start_main@GLIBC_2.17>
  400654:	91012000 	add	x0, x0, #0x48
  400658:	d0000081 	adrp	x1, 412000 <__libc_start_main@GLIBC_2.17>
  40065c:	91012021 	add	x1, x1, #0x48
  400660:	eb00003f 	cmp	x1, x0
  400664:	540000a0 	b.eq	400678 <deregister_tm_clones+0x28>  // b.none
  400668:	90000001 	adrp	x1, 400000 <_init-0x540>
  40066c:	f9478421 	ldr	x1, [x1, #3848]
  400670:	b4000041 	cbz	x1, 400678 <deregister_tm_clones+0x28>
  400674:	d61f0020 	br	x1
  400678:	d65f03c0 	ret
  40067c:	d503201f 	nop

0000000000400680 <register_tm_clones>:
  400680:	d0000080 	adrp	x0, 412000 <__libc_start_main@GLIBC_2.17>
  400684:	91012000 	add	x0, x0, #0x48
  400688:	d0000081 	adrp	x1, 412000 <__libc_start_main@GLIBC_2.17>
  40068c:	91012021 	add	x1, x1, #0x48
  400690:	cb000021 	sub	x1, x1, x0
  400694:	9343fc21 	asr	x1, x1, #3
  400698:	8b41fc21 	add	x1, x1, x1, lsr #63
  40069c:	9341fc21 	asr	x1, x1, #1
  4006a0:	b40000a1 	cbz	x1, 4006b4 <register_tm_clones+0x34>
  4006a4:	90000002 	adrp	x2, 400000 <_init-0x540>
  4006a8:	f9478842 	ldr	x2, [x2, #3856]
  4006ac:	b4000042 	cbz	x2, 4006b4 <register_tm_clones+0x34>
  4006b0:	d61f0040 	br	x2
  4006b4:	d65f03c0 	ret

00000000004006b8 <__do_global_dtors_aux>:
  4006b8:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  4006bc:	910003fd 	mov	x29, sp
  4006c0:	f9000bf3 	str	x19, [sp, #16]
  4006c4:	d0000093 	adrp	x19, 412000 <__libc_start_main@GLIBC_2.17>
  4006c8:	39412260 	ldrb	w0, [x19, #72]
  4006cc:	35000080 	cbnz	w0, 4006dc <__do_global_dtors_aux+0x24>
  4006d0:	97ffffe0 	bl	400650 <deregister_tm_clones>
  4006d4:	52800020 	mov	w0, #0x1                   	// #1
  4006d8:	39012260 	strb	w0, [x19, #72]
  4006dc:	f9400bf3 	ldr	x19, [sp, #16]
  4006e0:	a8c27bfd 	ldp	x29, x30, [sp], #32
  4006e4:	d65f03c0 	ret

00000000004006e8 <frame_dummy>:
  4006e8:	17ffffe6 	b	400680 <register_tm_clones>

00000000004006ec <undirected_graph>:
  4006ec:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  4006f0:	910003fd 	mov	x29, sp
  4006f4:	f9000fa0 	str	x0, [x29, #24]
  4006f8:	52800020 	mov	w0, #0x1                   	// #1
  4006fc:	b9002fa0 	str	w0, [x29, #44]
  400700:	1400000b 	b	40072c <undirected_graph+0x40>
  400704:	b9802fa0 	ldrsw	x0, [x29, #44]
  400708:	d37ef400 	lsl	x0, x0, #2
  40070c:	f9400fa1 	ldr	x1, [x29, #24]
  400710:	8b000021 	add	x1, x1, x0
  400714:	90000000 	adrp	x0, 400000 <_init-0x540>
  400718:	913c6000 	add	x0, x0, #0xf18
  40071c:	97ffffa9 	bl	4005c0 <__isoc99_scanf@plt>
  400720:	b9402fa0 	ldr	w0, [x29, #44]
  400724:	11000400 	add	w0, w0, #0x1
  400728:	b9002fa0 	str	w0, [x29, #44]
  40072c:	b9402fa0 	ldr	w0, [x29, #44]
  400730:	7100141f 	cmp	w0, #0x5
  400734:	54fffe8d 	b.le	400704 <undirected_graph+0x18>
  400738:	52800020 	mov	w0, #0x1                   	// #1
  40073c:	b9002ba0 	str	w0, [x29, #40]
  400740:	1400001b 	b	4007ac <undirected_graph+0xc0>
  400744:	52800020 	mov	w0, #0x1                   	// #1
  400748:	b90027a0 	str	w0, [x29, #36]
  40074c:	14000012 	b	400794 <undirected_graph+0xa8>
  400750:	b9402ba0 	ldr	w0, [x29, #40]
  400754:	b94027a1 	ldr	w1, [x29, #36]
  400758:	f9400fa2 	ldr	x2, [x29, #24]
  40075c:	93407c23 	sxtw	x3, w1
  400760:	93407c01 	sxtw	x1, w0
  400764:	aa0103e0 	mov	x0, x1
  400768:	d37ff800 	lsl	x0, x0, #1
  40076c:	8b010000 	add	x0, x0, x1
  400770:	d37ff800 	lsl	x0, x0, #1
  400774:	8b030000 	add	x0, x0, x3
  400778:	91001000 	add	x0, x0, #0x4
  40077c:	d37ef400 	lsl	x0, x0, #2
  400780:	8b000040 	add	x0, x2, x0
  400784:	b900081f 	str	wzr, [x0, #8]
  400788:	b94027a0 	ldr	w0, [x29, #36]
  40078c:	11000400 	add	w0, w0, #0x1
  400790:	b90027a0 	str	w0, [x29, #36]
  400794:	b94027a0 	ldr	w0, [x29, #36]
  400798:	7100141f 	cmp	w0, #0x5
  40079c:	54fffdad 	b.le	400750 <undirected_graph+0x64>
  4007a0:	b9402ba0 	ldr	w0, [x29, #40]
  4007a4:	11000400 	add	w0, w0, #0x1
  4007a8:	b9002ba0 	str	w0, [x29, #40]
  4007ac:	b9402ba0 	ldr	w0, [x29, #40]
  4007b0:	7100141f 	cmp	w0, #0x5
  4007b4:	54fffc8d 	b.le	400744 <undirected_graph+0x58>
  4007b8:	52800020 	mov	w0, #0x1                   	// #1
  4007bc:	b9002fa0 	str	w0, [x29, #44]
  4007c0:	1400002c 	b	400870 <undirected_graph+0x184>
  4007c4:	910093a2 	add	x2, x29, #0x24
  4007c8:	9100a3a1 	add	x1, x29, #0x28
  4007cc:	90000000 	adrp	x0, 400000 <_init-0x540>
  4007d0:	913c8000 	add	x0, x0, #0xf20
  4007d4:	97ffff7b 	bl	4005c0 <__isoc99_scanf@plt>
  4007d8:	b9402ba1 	ldr	w1, [x29, #40]
  4007dc:	b94027a2 	ldr	w2, [x29, #36]
  4007e0:	90000000 	adrp	x0, 400000 <_init-0x540>
  4007e4:	913ca000 	add	x0, x0, #0xf28
  4007e8:	97ffff7a 	bl	4005d0 <printf@plt>
  4007ec:	b9402ba0 	ldr	w0, [x29, #40]
  4007f0:	b94027a1 	ldr	w1, [x29, #36]
  4007f4:	f9400fa2 	ldr	x2, [x29, #24]
  4007f8:	93407c23 	sxtw	x3, w1
  4007fc:	93407c01 	sxtw	x1, w0
  400800:	aa0103e0 	mov	x0, x1
  400804:	d37ff800 	lsl	x0, x0, #1
  400808:	8b010000 	add	x0, x0, x1
  40080c:	d37ff800 	lsl	x0, x0, #1
  400810:	8b030000 	add	x0, x0, x3
  400814:	91001000 	add	x0, x0, #0x4
  400818:	d37ef400 	lsl	x0, x0, #2
  40081c:	8b000040 	add	x0, x2, x0
  400820:	52800021 	mov	w1, #0x1                   	// #1
  400824:	b9000801 	str	w1, [x0, #8]
  400828:	b94027a0 	ldr	w0, [x29, #36]
  40082c:	b9402ba1 	ldr	w1, [x29, #40]
  400830:	f9400fa2 	ldr	x2, [x29, #24]
  400834:	93407c23 	sxtw	x3, w1
  400838:	93407c01 	sxtw	x1, w0
  40083c:	aa0103e0 	mov	x0, x1
  400840:	d37ff800 	lsl	x0, x0, #1
  400844:	8b010000 	add	x0, x0, x1
  400848:	d37ff800 	lsl	x0, x0, #1
  40084c:	8b030000 	add	x0, x0, x3
  400850:	91001000 	add	x0, x0, #0x4
  400854:	d37ef400 	lsl	x0, x0, #2
  400858:	8b000040 	add	x0, x2, x0
  40085c:	52800021 	mov	w1, #0x1                   	// #1
  400860:	b9000801 	str	w1, [x0, #8]
  400864:	b9402fa0 	ldr	w0, [x29, #44]
  400868:	11000400 	add	w0, w0, #0x1
  40086c:	b9002fa0 	str	w0, [x29, #44]
  400870:	b9402fa0 	ldr	w0, [x29, #44]
  400874:	7100401f 	cmp	w0, #0x10
  400878:	54fffa6d 	b.le	4007c4 <undirected_graph+0xd8>
  40087c:	d503201f 	nop
  400880:	a8c37bfd 	ldp	x29, x30, [sp], #48
  400884:	d65f03c0 	ret

0000000000400888 <directed_graph>:
  400888:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  40088c:	910003fd 	mov	x29, sp
  400890:	f9000fa0 	str	x0, [x29, #24]
  400894:	52800020 	mov	w0, #0x1                   	// #1
  400898:	b9002fa0 	str	w0, [x29, #44]
  40089c:	1400000b 	b	4008c8 <directed_graph+0x40>
  4008a0:	b9802fa0 	ldrsw	x0, [x29, #44]
  4008a4:	d37ef400 	lsl	x0, x0, #2
  4008a8:	f9400fa1 	ldr	x1, [x29, #24]
  4008ac:	8b000021 	add	x1, x1, x0
  4008b0:	90000000 	adrp	x0, 400000 <_init-0x540>
  4008b4:	913c6000 	add	x0, x0, #0xf18
  4008b8:	97ffff42 	bl	4005c0 <__isoc99_scanf@plt>
  4008bc:	b9402fa0 	ldr	w0, [x29, #44]
  4008c0:	11000400 	add	w0, w0, #0x1
  4008c4:	b9002fa0 	str	w0, [x29, #44]
  4008c8:	b9402fa0 	ldr	w0, [x29, #44]
  4008cc:	7100141f 	cmp	w0, #0x5
  4008d0:	54fffe8d 	b.le	4008a0 <directed_graph+0x18>
  4008d4:	52800020 	mov	w0, #0x1                   	// #1
  4008d8:	b9002ba0 	str	w0, [x29, #40]
  4008dc:	1400001b 	b	400948 <directed_graph+0xc0>
  4008e0:	52800020 	mov	w0, #0x1                   	// #1
  4008e4:	b90027a0 	str	w0, [x29, #36]
  4008e8:	14000012 	b	400930 <directed_graph+0xa8>
  4008ec:	b9402ba0 	ldr	w0, [x29, #40]
  4008f0:	b94027a1 	ldr	w1, [x29, #36]
  4008f4:	f9400fa2 	ldr	x2, [x29, #24]
  4008f8:	93407c23 	sxtw	x3, w1
  4008fc:	93407c01 	sxtw	x1, w0
  400900:	aa0103e0 	mov	x0, x1
  400904:	d37ff800 	lsl	x0, x0, #1
  400908:	8b010000 	add	x0, x0, x1
  40090c:	d37ff800 	lsl	x0, x0, #1
  400910:	8b030000 	add	x0, x0, x3
  400914:	91001000 	add	x0, x0, #0x4
  400918:	d37ef400 	lsl	x0, x0, #2
  40091c:	8b000040 	add	x0, x2, x0
  400920:	b900081f 	str	wzr, [x0, #8]
  400924:	b94027a0 	ldr	w0, [x29, #36]
  400928:	11000400 	add	w0, w0, #0x1
  40092c:	b90027a0 	str	w0, [x29, #36]
  400930:	b94027a0 	ldr	w0, [x29, #36]
  400934:	7100141f 	cmp	w0, #0x5
  400938:	54fffdad 	b.le	4008ec <directed_graph+0x64>
  40093c:	b9402ba0 	ldr	w0, [x29, #40]
  400940:	11000400 	add	w0, w0, #0x1
  400944:	b9002ba0 	str	w0, [x29, #40]
  400948:	b9402ba0 	ldr	w0, [x29, #40]
  40094c:	7100141f 	cmp	w0, #0x5
  400950:	54fffc8d 	b.le	4008e0 <directed_graph+0x58>
  400954:	90000000 	adrp	x0, 400000 <_init-0x540>
  400958:	913ce000 	add	x0, x0, #0xf38
  40095c:	97ffff15 	bl	4005b0 <puts@plt>
  400960:	52800020 	mov	w0, #0x1                   	// #1
  400964:	b9002fa0 	str	w0, [x29, #44]
  400968:	14000018 	b	4009c8 <directed_graph+0x140>
  40096c:	910093a2 	add	x2, x29, #0x24
  400970:	9100a3a1 	add	x1, x29, #0x28
  400974:	90000000 	adrp	x0, 400000 <_init-0x540>
  400978:	913c8000 	add	x0, x0, #0xf20
  40097c:	97ffff11 	bl	4005c0 <__isoc99_scanf@plt>
  400980:	b9402ba0 	ldr	w0, [x29, #40]
  400984:	b94027a1 	ldr	w1, [x29, #36]
  400988:	f9400fa2 	ldr	x2, [x29, #24]
  40098c:	93407c23 	sxtw	x3, w1
  400990:	93407c01 	sxtw	x1, w0
  400994:	aa0103e0 	mov	x0, x1
  400998:	d37ff800 	lsl	x0, x0, #1
  40099c:	8b010000 	add	x0, x0, x1
  4009a0:	d37ff800 	lsl	x0, x0, #1
  4009a4:	8b030000 	add	x0, x0, x3
  4009a8:	91001000 	add	x0, x0, #0x4
  4009ac:	d37ef400 	lsl	x0, x0, #2
  4009b0:	8b000040 	add	x0, x2, x0
  4009b4:	52800021 	mov	w1, #0x1                   	// #1
  4009b8:	b9000801 	str	w1, [x0, #8]
  4009bc:	b9402fa0 	ldr	w0, [x29, #44]
  4009c0:	11000400 	add	w0, w0, #0x1
  4009c4:	b9002fa0 	str	w0, [x29, #44]
  4009c8:	b9402fa0 	ldr	w0, [x29, #44]
  4009cc:	7100401f 	cmp	w0, #0x10
  4009d0:	54fffced 	b.le	40096c <directed_graph+0xe4>
  4009d4:	d503201f 	nop
  4009d8:	a8c37bfd 	ldp	x29, x30, [sp], #48
  4009dc:	d65f03c0 	ret

00000000004009e0 <undirected_quan_graph>:
  4009e0:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  4009e4:	910003fd 	mov	x29, sp
  4009e8:	f9000fa0 	str	x0, [x29, #24]
  4009ec:	52800020 	mov	w0, #0x1                   	// #1
  4009f0:	b9002fa0 	str	w0, [x29, #44]
  4009f4:	1400000b 	b	400a20 <undirected_quan_graph+0x40>
  4009f8:	b9802fa0 	ldrsw	x0, [x29, #44]
  4009fc:	d37ef400 	lsl	x0, x0, #2
  400a00:	f9400fa1 	ldr	x1, [x29, #24]
  400a04:	8b000021 	add	x1, x1, x0
  400a08:	90000000 	adrp	x0, 400000 <_init-0x540>
  400a0c:	913c6000 	add	x0, x0, #0xf18
  400a10:	97fffeec 	bl	4005c0 <__isoc99_scanf@plt>
  400a14:	b9402fa0 	ldr	w0, [x29, #44]
  400a18:	11000400 	add	w0, w0, #0x1
  400a1c:	b9002fa0 	str	w0, [x29, #44]
  400a20:	b9402fa0 	ldr	w0, [x29, #44]
  400a24:	7100141f 	cmp	w0, #0x5
  400a28:	54fffe8d 	b.le	4009f8 <undirected_quan_graph+0x18>
  400a2c:	52800020 	mov	w0, #0x1                   	// #1
  400a30:	b9002ba0 	str	w0, [x29, #40]
  400a34:	1400002f 	b	400af0 <undirected_quan_graph+0x110>
  400a38:	52800020 	mov	w0, #0x1                   	// #1
  400a3c:	b90027a0 	str	w0, [x29, #36]
  400a40:	14000026 	b	400ad8 <undirected_quan_graph+0xf8>
  400a44:	b9402ba1 	ldr	w1, [x29, #40]
  400a48:	b94027a0 	ldr	w0, [x29, #36]
  400a4c:	6b00003f 	cmp	w1, w0
  400a50:	54000201 	b.ne	400a90 <undirected_quan_graph+0xb0>  // b.any
  400a54:	b9402ba0 	ldr	w0, [x29, #40]
  400a58:	b94027a1 	ldr	w1, [x29, #36]
  400a5c:	f9400fa2 	ldr	x2, [x29, #24]
  400a60:	93407c23 	sxtw	x3, w1
  400a64:	93407c01 	sxtw	x1, w0
  400a68:	aa0103e0 	mov	x0, x1
  400a6c:	d37ff800 	lsl	x0, x0, #1
  400a70:	8b010000 	add	x0, x0, x1
  400a74:	d37ff800 	lsl	x0, x0, #1
  400a78:	8b030000 	add	x0, x0, x3
  400a7c:	91001000 	add	x0, x0, #0x4
  400a80:	d37ef400 	lsl	x0, x0, #2
  400a84:	8b000040 	add	x0, x2, x0
  400a88:	b900081f 	str	wzr, [x0, #8]
  400a8c:	14000010 	b	400acc <undirected_quan_graph+0xec>
  400a90:	b9402ba0 	ldr	w0, [x29, #40]
  400a94:	b94027a1 	ldr	w1, [x29, #36]
  400a98:	f9400fa2 	ldr	x2, [x29, #24]
  400a9c:	93407c23 	sxtw	x3, w1
  400aa0:	93407c01 	sxtw	x1, w0
  400aa4:	aa0103e0 	mov	x0, x1
  400aa8:	d37ff800 	lsl	x0, x0, #1
  400aac:	8b010000 	add	x0, x0, x1
  400ab0:	d37ff800 	lsl	x0, x0, #1
  400ab4:	8b030000 	add	x0, x0, x3
  400ab8:	91001000 	add	x0, x0, #0x4
  400abc:	d37ef400 	lsl	x0, x0, #2
  400ac0:	8b000040 	add	x0, x2, x0
  400ac4:	5284e1e1 	mov	w1, #0x270f                	// #9999
  400ac8:	b9000801 	str	w1, [x0, #8]
  400acc:	b94027a0 	ldr	w0, [x29, #36]
  400ad0:	11000400 	add	w0, w0, #0x1
  400ad4:	b90027a0 	str	w0, [x29, #36]
  400ad8:	b94027a0 	ldr	w0, [x29, #36]
  400adc:	7100141f 	cmp	w0, #0x5
  400ae0:	54fffb2d 	b.le	400a44 <undirected_quan_graph+0x64>
  400ae4:	b9402ba0 	ldr	w0, [x29, #40]
  400ae8:	11000400 	add	w0, w0, #0x1
  400aec:	b9002ba0 	str	w0, [x29, #40]
  400af0:	b9402ba0 	ldr	w0, [x29, #40]
  400af4:	7100141f 	cmp	w0, #0x5
  400af8:	54fffa0d 	b.le	400a38 <undirected_quan_graph+0x58>
  400afc:	52800020 	mov	w0, #0x1                   	// #1
  400b00:	b9002fa0 	str	w0, [x29, #44]
  400b04:	14000028 	b	400ba4 <undirected_quan_graph+0x1c4>
  400b08:	910083a3 	add	x3, x29, #0x20
  400b0c:	910093a2 	add	x2, x29, #0x24
  400b10:	9100a3a1 	add	x1, x29, #0x28
  400b14:	90000000 	adrp	x0, 400000 <_init-0x540>
  400b18:	913d2000 	add	x0, x0, #0xf48
  400b1c:	97fffea9 	bl	4005c0 <__isoc99_scanf@plt>
  400b20:	b9402ba0 	ldr	w0, [x29, #40]
  400b24:	b94027a1 	ldr	w1, [x29, #36]
  400b28:	b94023a2 	ldr	w2, [x29, #32]
  400b2c:	f9400fa3 	ldr	x3, [x29, #24]
  400b30:	93407c24 	sxtw	x4, w1
  400b34:	93407c01 	sxtw	x1, w0
  400b38:	aa0103e0 	mov	x0, x1
  400b3c:	d37ff800 	lsl	x0, x0, #1
  400b40:	8b010000 	add	x0, x0, x1
  400b44:	d37ff800 	lsl	x0, x0, #1
  400b48:	8b040000 	add	x0, x0, x4
  400b4c:	91001000 	add	x0, x0, #0x4
  400b50:	d37ef400 	lsl	x0, x0, #2
  400b54:	8b000060 	add	x0, x3, x0
  400b58:	b9000802 	str	w2, [x0, #8]
  400b5c:	b94027a0 	ldr	w0, [x29, #36]
  400b60:	b9402ba1 	ldr	w1, [x29, #40]
  400b64:	b94023a2 	ldr	w2, [x29, #32]
  400b68:	f9400fa3 	ldr	x3, [x29, #24]
  400b6c:	93407c24 	sxtw	x4, w1
  400b70:	93407c01 	sxtw	x1, w0
  400b74:	aa0103e0 	mov	x0, x1
  400b78:	d37ff800 	lsl	x0, x0, #1
  400b7c:	8b010000 	add	x0, x0, x1
  400b80:	d37ff800 	lsl	x0, x0, #1
  400b84:	8b040000 	add	x0, x0, x4
  400b88:	91001000 	add	x0, x0, #0x4
  400b8c:	d37ef400 	lsl	x0, x0, #2
  400b90:	8b000060 	add	x0, x3, x0
  400b94:	b9000802 	str	w2, [x0, #8]
  400b98:	b9402fa0 	ldr	w0, [x29, #44]
  400b9c:	11000400 	add	w0, w0, #0x1
  400ba0:	b9002fa0 	str	w0, [x29, #44]
  400ba4:	b9402fa0 	ldr	w0, [x29, #44]
  400ba8:	7100401f 	cmp	w0, #0x10
  400bac:	54fffaed 	b.le	400b08 <undirected_quan_graph+0x128>
  400bb0:	d503201f 	nop
  400bb4:	a8c37bfd 	ldp	x29, x30, [sp], #48
  400bb8:	d65f03c0 	ret

0000000000400bbc <directed_quan_graph>:
  400bbc:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  400bc0:	910003fd 	mov	x29, sp
  400bc4:	f9000fa0 	str	x0, [x29, #24]
  400bc8:	52800020 	mov	w0, #0x1                   	// #1
  400bcc:	b9002fa0 	str	w0, [x29, #44]
  400bd0:	1400000b 	b	400bfc <directed_quan_graph+0x40>
  400bd4:	b9802fa0 	ldrsw	x0, [x29, #44]
  400bd8:	d37ef400 	lsl	x0, x0, #2
  400bdc:	f9400fa1 	ldr	x1, [x29, #24]
  400be0:	8b000021 	add	x1, x1, x0
  400be4:	90000000 	adrp	x0, 400000 <_init-0x540>
  400be8:	913c6000 	add	x0, x0, #0xf18
  400bec:	97fffe75 	bl	4005c0 <__isoc99_scanf@plt>
  400bf0:	b9402fa0 	ldr	w0, [x29, #44]
  400bf4:	11000400 	add	w0, w0, #0x1
  400bf8:	b9002fa0 	str	w0, [x29, #44]
  400bfc:	b9402fa0 	ldr	w0, [x29, #44]
  400c00:	7100141f 	cmp	w0, #0x5
  400c04:	54fffe8d 	b.le	400bd4 <directed_quan_graph+0x18>
  400c08:	52800020 	mov	w0, #0x1                   	// #1
  400c0c:	b9002ba0 	str	w0, [x29, #40]
  400c10:	14000030 	b	400cd0 <directed_quan_graph+0x114>
  400c14:	52800020 	mov	w0, #0x1                   	// #1
  400c18:	b90027a0 	str	w0, [x29, #36]
  400c1c:	14000027 	b	400cb8 <directed_quan_graph+0xfc>
  400c20:	b94027a0 	ldr	w0, [x29, #36]
  400c24:	b9002ba0 	str	w0, [x29, #40]
  400c28:	b9402ba0 	ldr	w0, [x29, #40]
  400c2c:	7100001f 	cmp	w0, #0x0
  400c30:	54000200 	b.eq	400c70 <directed_quan_graph+0xb4>  // b.none
  400c34:	b9402ba0 	ldr	w0, [x29, #40]
  400c38:	b94027a1 	ldr	w1, [x29, #36]
  400c3c:	f9400fa2 	ldr	x2, [x29, #24]
  400c40:	93407c23 	sxtw	x3, w1
  400c44:	93407c01 	sxtw	x1, w0
  400c48:	aa0103e0 	mov	x0, x1
  400c4c:	d37ff800 	lsl	x0, x0, #1
  400c50:	8b010000 	add	x0, x0, x1
  400c54:	d37ff800 	lsl	x0, x0, #1
  400c58:	8b030000 	add	x0, x0, x3
  400c5c:	91001000 	add	x0, x0, #0x4
  400c60:	d37ef400 	lsl	x0, x0, #2
  400c64:	8b000040 	add	x0, x2, x0
  400c68:	b900081f 	str	wzr, [x0, #8]
  400c6c:	14000010 	b	400cac <directed_quan_graph+0xf0>
  400c70:	b9402ba0 	ldr	w0, [x29, #40]
  400c74:	b94027a1 	ldr	w1, [x29, #36]
  400c78:	f9400fa2 	ldr	x2, [x29, #24]
  400c7c:	93407c23 	sxtw	x3, w1
  400c80:	93407c01 	sxtw	x1, w0
  400c84:	aa0103e0 	mov	x0, x1
  400c88:	d37ff800 	lsl	x0, x0, #1
  400c8c:	8b010000 	add	x0, x0, x1
  400c90:	d37ff800 	lsl	x0, x0, #1
  400c94:	8b030000 	add	x0, x0, x3
  400c98:	91001000 	add	x0, x0, #0x4
  400c9c:	d37ef400 	lsl	x0, x0, #2
  400ca0:	8b000040 	add	x0, x2, x0
  400ca4:	5284e1e1 	mov	w1, #0x270f                	// #9999
  400ca8:	b9000801 	str	w1, [x0, #8]
  400cac:	b94027a0 	ldr	w0, [x29, #36]
  400cb0:	11000400 	add	w0, w0, #0x1
  400cb4:	b90027a0 	str	w0, [x29, #36]
  400cb8:	b94027a0 	ldr	w0, [x29, #36]
  400cbc:	7100141f 	cmp	w0, #0x5
  400cc0:	54fffb0d 	b.le	400c20 <directed_quan_graph+0x64>
  400cc4:	b9402ba0 	ldr	w0, [x29, #40]
  400cc8:	11000400 	add	w0, w0, #0x1
  400ccc:	b9002ba0 	str	w0, [x29, #40]
  400cd0:	b9402ba0 	ldr	w0, [x29, #40]
  400cd4:	7100141f 	cmp	w0, #0x5
  400cd8:	54fff9ed 	b.le	400c14 <directed_quan_graph+0x58>
  400cdc:	52800020 	mov	w0, #0x1                   	// #1
  400ce0:	b9002fa0 	str	w0, [x29, #44]
  400ce4:	14000019 	b	400d48 <directed_quan_graph+0x18c>
  400ce8:	910083a3 	add	x3, x29, #0x20
  400cec:	910093a2 	add	x2, x29, #0x24
  400cf0:	9100a3a1 	add	x1, x29, #0x28
  400cf4:	90000000 	adrp	x0, 400000 <_init-0x540>
  400cf8:	913d2000 	add	x0, x0, #0xf48
  400cfc:	97fffe31 	bl	4005c0 <__isoc99_scanf@plt>
  400d00:	b9402ba0 	ldr	w0, [x29, #40]
  400d04:	b94027a1 	ldr	w1, [x29, #36]
  400d08:	b94023a2 	ldr	w2, [x29, #32]
  400d0c:	f9400fa3 	ldr	x3, [x29, #24]
  400d10:	93407c24 	sxtw	x4, w1
  400d14:	93407c01 	sxtw	x1, w0
  400d18:	aa0103e0 	mov	x0, x1
  400d1c:	d37ff800 	lsl	x0, x0, #1
  400d20:	8b010000 	add	x0, x0, x1
  400d24:	d37ff800 	lsl	x0, x0, #1
  400d28:	8b040000 	add	x0, x0, x4
  400d2c:	91001000 	add	x0, x0, #0x4
  400d30:	d37ef400 	lsl	x0, x0, #2
  400d34:	8b000060 	add	x0, x3, x0
  400d38:	b9000802 	str	w2, [x0, #8]
  400d3c:	b9402fa0 	ldr	w0, [x29, #44]
  400d40:	11000400 	add	w0, w0, #0x1
  400d44:	b9002fa0 	str	w0, [x29, #44]
  400d48:	b9402fa0 	ldr	w0, [x29, #44]
  400d4c:	7100401f 	cmp	w0, #0x10
  400d50:	54fffccd 	b.le	400ce8 <directed_quan_graph+0x12c>
  400d54:	d503201f 	nop
  400d58:	a8c37bfd 	ldp	x29, x30, [sp], #48
  400d5c:	d65f03c0 	ret

0000000000400d60 <display>:
  400d60:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  400d64:	910003fd 	mov	x29, sp
  400d68:	f9000fa0 	str	x0, [x29, #24]
  400d6c:	b90017a1 	str	w1, [x29, #20]
  400d70:	b90027bf 	str	wzr, [x29, #36]
  400d74:	52800020 	mov	w0, #0x1                   	// #1
  400d78:	b9002fa0 	str	w0, [x29, #44]
  400d7c:	14000029 	b	400e20 <display+0xc0>
  400d80:	52800020 	mov	w0, #0x1                   	// #1
  400d84:	b9002ba0 	str	w0, [x29, #40]
  400d88:	14000020 	b	400e08 <display+0xa8>
  400d8c:	f9400fa2 	ldr	x2, [x29, #24]
  400d90:	b9802ba3 	ldrsw	x3, [x29, #40]
  400d94:	b9802fa1 	ldrsw	x1, [x29, #44]
  400d98:	aa0103e0 	mov	x0, x1
  400d9c:	d37ff800 	lsl	x0, x0, #1
  400da0:	8b010000 	add	x0, x0, x1
  400da4:	d37ff800 	lsl	x0, x0, #1
  400da8:	8b030000 	add	x0, x0, x3
  400dac:	91001000 	add	x0, x0, #0x4
  400db0:	d37ef400 	lsl	x0, x0, #2
  400db4:	8b000040 	add	x0, x2, x0
  400db8:	b9400801 	ldr	w1, [x0, #8]
  400dbc:	90000000 	adrp	x0, 400000 <_init-0x540>
  400dc0:	913d6000 	add	x0, x0, #0xf58
  400dc4:	97fffe03 	bl	4005d0 <printf@plt>
  400dc8:	b94027a0 	ldr	w0, [x29, #36]
  400dcc:	11000400 	add	w0, w0, #0x1
  400dd0:	b90027a0 	str	w0, [x29, #36]
  400dd4:	b94027a0 	ldr	w0, [x29, #36]
  400dd8:	b94017a1 	ldr	w1, [x29, #20]
  400ddc:	1ac10c02 	sdiv	w2, w0, w1
  400de0:	b94017a1 	ldr	w1, [x29, #20]
  400de4:	1b017c41 	mul	w1, w2, w1
  400de8:	4b010000 	sub	w0, w0, w1
  400dec:	7100001f 	cmp	w0, #0x0
  400df0:	54000061 	b.ne	400dfc <display+0x9c>  // b.any
  400df4:	52800140 	mov	w0, #0xa                   	// #10
  400df8:	97fffdfa 	bl	4005e0 <putchar@plt>
  400dfc:	b9402ba0 	ldr	w0, [x29, #40]
  400e00:	11000400 	add	w0, w0, #0x1
  400e04:	b9002ba0 	str	w0, [x29, #40]
  400e08:	b9402ba0 	ldr	w0, [x29, #40]
  400e0c:	7100141f 	cmp	w0, #0x5
  400e10:	54fffbed 	b.le	400d8c <display+0x2c>
  400e14:	b9402fa0 	ldr	w0, [x29, #44]
  400e18:	11000400 	add	w0, w0, #0x1
  400e1c:	b9002fa0 	str	w0, [x29, #44]
  400e20:	b9402fa0 	ldr	w0, [x29, #44]
  400e24:	7100141f 	cmp	w0, #0x5
  400e28:	54fffacd 	b.le	400d80 <display+0x20>
  400e2c:	52800140 	mov	w0, #0xa                   	// #10
  400e30:	97fffdec 	bl	4005e0 <putchar@plt>
  400e34:	d503201f 	nop
  400e38:	a8c37bfd 	ldp	x29, x30, [sp], #48
  400e3c:	d65f03c0 	ret

0000000000400e40 <main>:
  400e40:	a9b47bfd 	stp	x29, x30, [sp, #-192]!
  400e44:	910003fd 	mov	x29, sp
  400e48:	910063a0 	add	x0, x29, #0x18
  400e4c:	97fffee5 	bl	4009e0 <undirected_quan_graph>
  400e50:	910063a0 	add	x0, x29, #0x18
  400e54:	528000a1 	mov	w1, #0x5                   	// #5
  400e58:	97ffffc2 	bl	400d60 <display>
  400e5c:	52800000 	mov	w0, #0x0                   	// #0
  400e60:	a8cc7bfd 	ldp	x29, x30, [sp], #192
  400e64:	d65f03c0 	ret

0000000000400e68 <__libc_csu_init>:
  400e68:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  400e6c:	910003fd 	mov	x29, sp
  400e70:	a901d7f4 	stp	x20, x21, [sp, #24]
  400e74:	b0000094 	adrp	x20, 411000 <__FRAME_END__+0x100a0>
  400e78:	b0000095 	adrp	x21, 411000 <__FRAME_END__+0x100a0>
  400e7c:	91374294 	add	x20, x20, #0xdd0
  400e80:	913722b5 	add	x21, x21, #0xdc8
  400e84:	a902dff6 	stp	x22, x23, [sp, #40]
  400e88:	cb150294 	sub	x20, x20, x21
  400e8c:	f9001ff8 	str	x24, [sp, #56]
  400e90:	2a0003f6 	mov	w22, w0
  400e94:	aa0103f7 	mov	x23, x1
  400e98:	9343fe94 	asr	x20, x20, #3
  400e9c:	aa0203f8 	mov	x24, x2
  400ea0:	97fffda8 	bl	400540 <_init>
  400ea4:	b4000194 	cbz	x20, 400ed4 <__libc_csu_init+0x6c>
  400ea8:	f9000bb3 	str	x19, [x29, #16]
  400eac:	d2800013 	mov	x19, #0x0                   	// #0
  400eb0:	f8737aa3 	ldr	x3, [x21, x19, lsl #3]
  400eb4:	aa1803e2 	mov	x2, x24
  400eb8:	aa1703e1 	mov	x1, x23
  400ebc:	2a1603e0 	mov	w0, w22
  400ec0:	91000673 	add	x19, x19, #0x1
  400ec4:	d63f0060 	blr	x3
  400ec8:	eb13029f 	cmp	x20, x19
  400ecc:	54ffff21 	b.ne	400eb0 <__libc_csu_init+0x48>  // b.any
  400ed0:	f9400bb3 	ldr	x19, [x29, #16]
  400ed4:	a941d7f4 	ldp	x20, x21, [sp, #24]
  400ed8:	a942dff6 	ldp	x22, x23, [sp, #40]
  400edc:	f9401ff8 	ldr	x24, [sp, #56]
  400ee0:	a8c47bfd 	ldp	x29, x30, [sp], #64
  400ee4:	d65f03c0 	ret

0000000000400ee8 <__libc_csu_fini>:
  400ee8:	d65f03c0 	ret

Disassembly of section .fini:

0000000000400eec <_fini>:
  400eec:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  400ef0:	910003fd 	mov	x29, sp
  400ef4:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400ef8:	d65f03c0 	ret
